Atsushi Nemoto wrote:
Hmm, I got it: you decide whether it's worth waiting more for XFEREND
interrupt based on whether ERR is set or not. I suppose IDE_INT doesn't get
set in case the command gets endede with ERR set?
Well, let me explain a bit. The datasheed say I should wait _both_
XFERINT and HOST interrupt. So, if only one of them was asserted, I
mask it and wait another one. But on the error case, only HOST was
asserted and XFERINT was never asserted. Then I could not exit from
"waiting another one" state, until timeout.
IIRC, yes. And anyway, the interrupt signal from this controller to
Thats wrong -- According t the spec. the bit should be set following any
assertion of INTRQ on IDE bus (possibly not at once though -- after
flushing FIFO). Well, no wonder with such description of the bits as:
INT_IDE (RWC) [Interrupt]
Is “1” when data transfer completes. This bit is cleared by writing “1”
When this bit is set to ‘1’, the following bits of the ATA Interrupt
Controller Register will be
reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT,
Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus
Data Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End,
CPU is not asserted because HOSTINT was masked by int_ctl register to
wait for XFERINT interrupt.
So, regardless of IDE_INT was set or not, no more interrupt raised to
Ah, it gets purposedly masked out...
Many of strangeness of interrupt handling in this driver is based on
the fact that the IDE_INT bit in DMA status register does not refrect
the controllers interrupt status directly.
It also seems to reflect the wrong status, i.e. that of the XFEREND
And the implementation of
the IDE_INT bit is actually broken. Claring the IDE_INT bit also
clears all mask bits in int_ctl registers. Usually this sort of
behaviour is called "bug". ;)
Hm, I thought that was done on purpose to "accelerate" interrupt
handling or something... it can help indeed if you're not masking those