| To: | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Subject: | Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec |
| From: | tsbogend@alpha.franken.de (Thomas Bogendoerfer) |
| Date: | Wed, 10 Sep 2008 10:31:57 +0200 |
| Cc: | ralf@linux-mips.org, ths@networkno.de, linux-mips@linux-mips.org, michael@free-electrons.com |
| In-reply-to: | <1220948125-3550-1-git-send-email-thomas.petazzoni@free-electrons.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1220948125-3550-1-git-send-email-thomas.petazzoni@free-electrons.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.13 (2006-08-11) |
On Tue, Sep 09, 2008 at 10:15:25AM +0200, Thomas Petazzoni wrote:
> + else {
> + clear_c0_cause(CAUSEF_IV);
> + }
so we now touch a bit, which is at least marked reserved for R10k CPUs
and hope nobody did something else with it ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
|
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec, Thomas Petazzoni |
|---|---|
| Next by Date: | Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec, Kevin D. Kissell |
| Previous by Thread: | [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec, Thomas Petazzoni |
| Next by Thread: | Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec, Kevin D. Kissell |
| Indexes: | [Date] [Thread] [Top] [All Lists] |