| To: | linux-mips@linux-mips.org |
|---|---|
| Subject: | Re: [Patch 0/6] MIPS: Hardware watch register support for gdb (version 3). |
| From: | David Daney <ddaney@avtrex.com> |
| Date: | Sat, 30 Aug 2008 01:37:05 -0700 |
| Cc: | linux-kernel@vger.kernel.org |
| In-reply-to: | <48B71ADD.601@avtrex.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <48B71ADD.601@avtrex.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Thunderbird 2.0.0.16 (X11/20080723) |
David Daney wrote: > Esteemed kernel hackers, > > To follow is my third pass at MIPS watch register support. > I think there will have to be at least one more pass at this. The current design assumes that all debug registers support an identical set of the I, R, and W bits and Mask. However sections 8.23 and 8.24 of my MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture indicate that they do not have to uniform. I will have to augment the ptrace structures to report the values for each register instead of a single global value. David Daney |
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