On Mon, Aug 25, 2008 at 09:34:29AM -0700, David Daney wrote:
> What is the reasoning for only doing the cache operation on R10K based
non coherent R10k need after DMA operations to get rid of remains
of load/store speculations. Other CPUs don't pollute the cache
after it got flushed.
But this optimization is wrong, we need to do the flush for
every non coherent device otherwise polling a descriptor via
a cached mapping can't work. And this exactly what E100 does.
Instead of if (cpu_is_noncoherent_r10000(deva)) something like
if (cpu_is_noncoherent_r10000(dev) ||
(!plat_device_is_coherent(dev) && (direction != DMA_TO_DEVICE)))
should do the trick with minimum flushes for non R10k CPUs. But probably
is the safest approach.
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]