linux-mips
[Top] [All Lists]

Config7.WII and IPI mechanism in SMTC linux

To: linux-mips@linux-mips.org
Subject: Config7.WII and IPI mechanism in SMTC linux
From: "Chung-Chi Lo" <linolo@gmail.com>
Date: Thu, 31 Jul 2008 14:41:06 +0800
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type:content-transfer-encoding :content-disposition; bh=/quVvWTXxzPh/ctO58PQ+yI3CdD5vspqjyztzMbXYY8=; b=JxCSBzZdW1D14CkWQ6Fq8tYCf3NXuj7m0/bNPZBeQ5rXvA4K/y1UHmNnyf+lLBWIuS iEeGxfTi8csMYYYL06jTw2yP0ajsGBGgrbZL4OVc57K1c4JgjbJo4L6eOLDvi0z7Nb+7 zNJ/fyAry5LOR79eJGpdxNHVc0r9RWqgGQyOw=
Domainkey-signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition; b=JvnqB9nF/09gx1Rc3tQnFXpzFKqR74ngXmOKj+FBr/MFT6X/W/prEkP2jyv95PBMxu P6Hhn4i5x7jU52Bo9cbddpWMJNUfyta3hqMNnD5LcntR9GouS9qSVgExcRHKyOdBvapn /bV3Sq/Bfe3OzJI7qZSZ4zhPAnnnkAXKOzm3w=
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hello,

My platform is MIPS 34K cpu core and Config7.WII=1.

If Config7.WII=1 and a TC is idle, the TC will execute "wait"
instruction with TCSTATUS.IXMT=1
to disable interrupt.

But in 34K, interrupts are not TC-specific. So some TCs will not get
real interrupts to break "wait"
instruction. Even in SMTC's IPI mechanism, the IPI mechanism is to
program TCRestart if target
TC is in the same VPE.

In function smtc_send_ipi, it detects if TC's interrupt is disabled,
then enqueue IPI message to
target TC's queue. So some TCs are always idle and cannot break "wait"
instruction. I don't know
if I miss something and please comment on this problem. Thanks.

                if ((tcstatus & TCSTATUS_IXMT) != 0) {
                        /*
                         * Spin-waiting here can deadlock,
                         * so we queue the message for the target TC.
                         */
                        write_tc_c0_tchalt(0);
                        UNLOCK_CORE_PRA();
                        .....
                        smtc_ipi_nq(&IPIQ[cpu], pipi);
                }

--
Lino, Chung-Chi Lo

<Prev in Thread] Current Thread [Next in Thread>
  • Config7.WII and IPI mechanism in SMTC linux, Chung-Chi Lo <=