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Re: [PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES

To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: Re: [PATCH] IP22: Fix crashes due to wrong L1_CACHE_BYTES
From: Ralf Baechle <ralf@linux-mips.org>
Date: Sat, 28 Jun 2008 20:25:09 +0200
Cc: linux-mips@linux-mips.org
In-reply-to: <20080627215226.D1B5EE2F71@solo.franken.de>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20080627215226.D1B5EE2F71@solo.franken.de>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.17 (2007-11-01)
On Fri, Jun 27, 2008 at 11:52:26PM +0200, Thomas Bogendoerfer wrote:

> The introduction of a real dma cache invalidate makes it important
> to have a correct cache line size, otherwise the kernel will gives
> out two memory segment, which might share one cache line. The R4400
> Indy/Indigo2 CPU modules are using a second level cache line size
> of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
> IP22.

Thanks, applied.

I also think this missconfiguration is worth an additional runtime
check; the consequence of that kind of bug are subtle and painful to
debug.

  Ralf

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