linux-mips
[Top] [All Lists]

[PATCH] cevt-txx9: Reset timer counter on initialize

To: linux-mips@linux-mips.org
Subject: [PATCH] cevt-txx9: Reset timer counter on initialize
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Tue, 24 Jun 2008 23:26:38 +0900 (JST)
Cc: ralf@linux-mips.org
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
The txx9_tmr_init() will not clear a timer counter register on certain
case.  The counter register is cleared on 1->0 transition of TCE bit
if CRE=1.  So just clearing TCE bit is not enough.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8f..b5fc4eb 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
        struct txx9_tmr_reg __iomem *tmrptr;
 
        tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
+       /* Start once to make CounterResetEnable effective */
+       __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
+       /* Stop and reset the counter */
        __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
        __raw_writel(0, &tmrptr->tisr);
        __raw_writel(0xffffffff, &tmrptr->cpra);

<Prev in Thread] Current Thread [Next in Thread>