Re: Changing the treatment of the MIPS HI and LO registers

[Paolo Bonzini <bonzini@gnu.org>]

> GLIBC contains the following code in stdlib/longlong.h:
> <snip>
> #if defined (__mips__) && W_TYPE_SIZE == 32
> #define umul_ppmm(w1, w0, u, v) \
>   __asm__ ("multu %2,%3"                        \
>        : "=l" ((USItype) (w0)),                    \
>          "=h" ((USItype) (w1))                    \
>        : "d" ((USItype) (u)),                    \
>          "d" ((USItype) (v)))
> #define UMUL_TIME 10
> #define UDIV_TIME 100
> #endif /* __mips__ */
> </snip>
Actually, so does GCC itself.  Can you prepare a patch?

> What would be a correct fix in this case?  Something like this:
> <snip>
> #define umul_ppmm(w1, w0, u, v)                    \
>   ({unsigned int __attribute__((mode(DI))) __xx;        \
>     __xx = (unsigned int __attribute__((mode(DI)))) u * v;    \
>     w0 = __xx & ((1 << 32) - 1);                \
>     w1 = __xx >> 32;})
> </snip>
>
> Or is there a better way?
Almost; this:

#define umul_ppmm(w1, w0, u, v)  \
  ({UDWtype __xx;                \
    UWtype __u = (u), __v = (v); \
    __xx = (UDWtype) __u * __v;  \
    w0 = (UWtype) __xx;          \
    w1 = __xx >> 32;})

should work.

Paolo