| To: | Sergei Shtylyov <sshtylyov@ru.mvista.com> |
|---|---|
| Subject: | Re: [PATCH] Alchemy: don't unmask timer IRQ early |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Tue, 25 Mar 2008 18:51:22 +0000 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <200803242315.50423.sshtylyov@ru.mvista.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <200803242315.50423.sshtylyov@ru.mvista.com> |
| Resent-date: | Wed, 26 Mar 2008 14:18:53 +0000 |
| Resent-from: | ralf@linux-mips.org |
| Resent-message-id: | <20080326141853.GA4017@linux-mips.org> |
| Resent-to: | linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.17 (2007-11-01) |
On Mon, Mar 24, 2008 at 11:15:50PM +0300, Sergei Shtylyov wrote: > Defer the unmasking of the count/compare interrupt (IRQ5) till the clockevent > driver initialization: > > - only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the ALLINTS > macro -- this change is blessed by AMD as I saw it in their own patch; :-) > > - do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's > no 32 KHz crystal. > > Update the copyrights (taking into account my prior changes), also removing > Pete Popov's old email... Queued for 2.6.26. Thanks, Ralf |
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