linux-mips
[Top] [All Lists]

Re: Tester with IP27/IP30 needed

To: Kumba <kumba@gentoo.org>
Subject: Re: Tester with IP27/IP30 needed
From: Thiemo Seufer <ths@networkno.de>
Date: Tue, 5 Feb 2008 12:22:11 +0000
Cc: Florian Lohoff <flo@rfc822.org>, Ralf Baechle <ralf@linux-mips.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>, linux-mips@linux-mips.org, debian-mips@lists.debian.org
In-reply-to: <47A80C0A.4040106@gentoo.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20080115112719.GB7920@paradigm.rfc822.org> <20080117004054.GA12051@alpha.franken.de> <479609A6.2020204@gentoo.org> <20080122154958.GA29108@linux-mips.org> <479AA532.5040603@gentoo.org> <20080126143949.GA6579@alpha.franken.de> <47A4E9DF.5070603@gentoo.org> <20080203021647.GA15910@linux-mips.org> <20080203062711.GA28394@paradigm.rfc822.org> <47A80C0A.4040106@gentoo.org>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.17+20080114 (2008-01-14)
Kumba wrote:
> Florian Lohoff wrote:
>> On Sun, Feb 03, 2008 at 03:16:48AM +0100, Ralf Baechle wrote:
>>> On Sat, Feb 02, 2008 at 05:08:31PM -0500, Kumba wrote:
>>>
>>>> Thomas Bogendoerfer wrote:
>>>>> no suprise here. As Ralf already noted cache barrier is a restricted
>>>>> instruction, it will always cause a illegal instruction when used
>>>>> in user space. Nevertheless it looks like all IP28 are affected
>>>>> by the simple exploit. Flo built glibc 2.7 with LLSC war workaround
>>>>> and this avoids triggering the hang.
>>>> Ah, didn't know the 'cache' instructions was kernel-mode only.  
>>>> Explains why it survived then :)
>>>>
>>>> How does one enable the LLSC war workaround in glibc?
>>> By modifying the code ;-)
>>
>> http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=462112
>>
>> Flo
>
> Interesting.  Is there a reason the kernel uses an #ifdef to choose 
> between 'bezq' and 'bezql' that's not needed in glibc itself?  Or does 
> glibc itself lack a mechanism to detect CPU types to single out this 
> specific change?

glibc for mips has currently no such mechanism. Note that this change
breaks MIPS I CPUs, so it is not generally applicable.

> And any idea if uClibc will need similar mods?

It needs a similiar change to support R10000 v2.5.


Thiemo

<Prev in Thread] Current Thread [Next in Thread>