Re: Tester with IP27/IP30 needed

[Ralf Baechle <ralf@linux-mips.org>]

On Sat, Feb 02, 2008 at 05:08:31PM -0500, Kumba wrote:

> 
> Thomas Bogendoerfer wrote:
>> no suprise here. As Ralf already noted cache barrier is a restricted
>> instruction, it will always cause a illegal instruction when used
>> in user space. Nevertheless it looks like all IP28 are affected
>> by the simple exploit. Flo built glibc 2.7 with LLSC war workaround
>> and this avoids triggering the hang.
>
> Ah, didn't know the 'cache' instructions was kernel-mode only.  Explains 
> why it survived then :)
>
> How does one enable the LLSC war workaround in glibc?

By modifying the code ;-)

  Ralf