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Re: quick question on 64-bit values with 32-bit inline assembly

To: ralf@linux-mips.org
Subject: Re: quick question on 64-bit values with 32-bit inline assembly
From: "M. Warner Losh" <imp@bsdimp.com>
Date: Mon, 28 Jan 2008 14:02:45 -0700 (MST)
Cc: cfriesen@nortel.com, linux-mips@linux-mips.org
In-reply-to: <20080122200751.GA2672@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20080122175734.GA31013@linux-mips.org> <47963C31.2000403@nortel.com> <20080122200751.GA2672@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
In message: <20080122200751.GA2672@linux-mips.org>
            Ralf Baechle <ralf@linux-mips.org> writes:
: On Tue, Jan 22, 2008 at 12:55:45PM -0600, Chris Friesen wrote:
: 
: >>> gethrtime(void)
: >>> {
: >>>   unsigned long long result;
: >>>
: >>>   asm volatile ("rdhwr %0,$31" : "=r" (result));
: >
: >> Ah, Cavium.
: >
: > Yes indeed.  Any peculiarities that we should be watching out for? Previous 
: > mailing list threads would be great.
: 
: Cavium so far received little coverage on this list - but seems you're
: about to start this.  The reason why I was able to identify Cavium is that
: afaics only Cavium is the only 64-bit CPU to implement a 64-bit timer in
: hardware register $31.
: 
: The definition of rdhwr is generic and I think if anybody has considered
: this specific interaction of ABI and processor architecture then it was
: probably found not to implement such a special read because it is messy
: in more than one way.

When 64-bit operations are enabled, you get all 64-bits.  When they
aren't, only the lower 32-bits of the counter are provided (with sign
extension).  So when operating in 32-bit mode, saving the upper 32
bits are not necessary (or even possible).

Warner

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