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Re: quick question on 64-bit values with 32-bit inline assembly

To: Chris Friesen <cfriesen@nortel.com>
Subject: Re: quick question on 64-bit values with 32-bit inline assembly
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 22 Jan 2008 20:07:51 +0000
Cc: linux-mips@linux-mips.org
In-reply-to: <47963C31.2000403@nortel.com>
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References: <4794DFE1.5040805@nortel.com> <20080122175734.GA31013@linux-mips.org> <47963C31.2000403@nortel.com>
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On Tue, Jan 22, 2008 at 12:55:45PM -0600, Chris Friesen wrote:

>>> gethrtime(void)
>>> {
>>>   unsigned long long result;
>>>
>>>   asm volatile ("rdhwr %0,$31" : "=r" (result));
>
>> Ah, Cavium.
>
> Yes indeed.  Any peculiarities that we should be watching out for? Previous 
> mailing list threads would be great.

Cavium so far received little coverage on this list - but seems you're
about to start this.  The reason why I was able to identify Cavium is that
afaics only Cavium is the only 64-bit CPU to implement a 64-bit timer in
hardware register $31.

The definition of rdhwr is generic and I think if anybody has considered
this specific interaction of ABI and processor architecture then it was
probably found not to implement such a special read because it is messy
in more than one way.

  Ralf

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