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Re: Linux mips and DMA

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Linux mips and DMA
From: Jon Dufresne <jon.dufresne@infinitevideocorporation.com>
Date: Thu, 10 Jan 2008 10:04:29 -0500
Cc: linux-mips@linux-mips.org
In-reply-to: <20080110143142.GA13210@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1199905038.3572.8.camel@microwave.infinitevideocorporation.com> <20080110113931.GA4774@linux-mips.org> <1199971818.4344.5.camel@microwave.infinitevideocorporation.com> <20080110134634.GA12060@linux-mips.org> <1199974344.4344.16.camel@microwave.infinitevideocorporation.com> <20080110143142.GA13210@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
> What you were doing seemed to be the right thing.  The API is supposed
> to do the necessary address conversion and cache flushes for the driver.
> That is the unchanged driver should work on any architecture.

> 
> According to the current kernel code the PNX8550 non-coheren (aka software
> coherency).
> 

Thanks Ralf,

So it sounds like you're saying even though my platform does not have HW
coherency, it shouldn't affect the driver code.

In my code, the device creates an interrupt when a message is to be
passed to the host. The message is written in the DMA memory. When I
receive that interrupt, is there some sort of flush I should do to
update the memory the cpu sees, with the data written by the device?

As of right now when I receive the interrupt, then inspect the dma
memory it appears as though nothing was written to memory. So at this
point I left thinking either the device can't correctly write to the
memory, or the memory isn't ready to be read by the host. I am having
trouble discovering which case is actually occurring.

Jon


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