On Thu, Jan 10, 2008 at 09:12:23AM -0500, Jon Dufresne wrote:
> > Hardware coherency for DMA is the exception for low-end embedded MIPS
> > systems andgiven the CPU address your's is no exception from that.
> > If your system was supporting hardware coherency for DMA I/O you would
> > have obtained a cachable CPU address like:
> > dma_handle=0x026f0000 size=0x00010000 cpu_addr=0x826f0000
> > ^^^
> > A 0x8??????? would be in KSEG0 so cachable.
> I do have a an embedded system. Are you saying that, in all likelyhood,
> I do not have coherency? If I understand you correctly, this is a bad
> thing right? Will I need to take extra care to work around this issue.
> So are you saying I would prefer a cpu_addr in the 0x8******* range?
No. because you don't seem to have hw coherency.
> If it is true that I don't have hardware coherency should I still be
> using the pci_*_consistent api? Or should I switch to the
> dma_*_noncoherent api? Also what extra steps do I need to take to get
> this to work with a non-coherent system?
What you were doing seemed to be the right thing. The API is supposed
to do the necessary address conversion and cache flushes for the driver.
That is the unchanged driver should work on any architecture.
The dma_* API is a generalization of the slightly older pci_* API. You
can use either one for a PCI device.
In fact on MIPS the pci_* functions are just wrappers around their dma_*
> I am reading Documentation/DMA-API.txt which has some discussion about
> non-coherent systems to see if I can get a handle on this.
> > What hardware are you using anyway?
> I am using the MDS-810 platform supplied by Momentum Data Systems which
> contains a Phillips/Nexperia pnx8950 chip. That chip contains a MIPS32
> core. http://www.mds.com/products/product.asp?prod=MDS-810
According to the current kernel code the PNX8550 non-coheren (aka software