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Re: kseg1 uncache access issue

To: lovecentry <lovecentry@gmail.com>
Subject: Re: kseg1 uncache access issue
From: tsbogend@alpha.franken.de (Thomas Bogendoerfer)
Date: Tue, 8 Jan 2008 18:02:06 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <4783a652.1cef600a.2530.fffffe31@mx.google.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4783a652.1cef600a.2530.fffffe31@mx.google.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.13 (2006-08-11)
On Wed, Jan 09, 2008 at 12:35:06AM +0800, lovecentry wrote:
> As we know in mips achitecture if current pc falls into kseg1 segment, any
> memory reference will bypass cache and fetch directly from dram. But for
> some prcoessor such like mips R10K it has off chip L2 cache. I haven't found

why do you think so ? R10k L2 cache controller is inside CPU and any
access with uncached attribute will go directly to memory. The only
systems, where this might be different are systems with caches unknown
to the cpu. But even those usually obey that uncached accesses are
going directly to memory.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

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