| To: | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Subject: | Re: [PATCH] Add code to determine the L2 cache size on Sibyte 1250/112x processors. |
| From: | Andrew Sharp <andy.sharp@onstor.com> |
| Date: | Mon, 3 Dec 2007 11:36:18 -0800 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20071203192010.GA14818@linux-mips.org> |
| Organization: | Onstor |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20071203175601.GA26533@onstor.com> <20071203192010.GA14818@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Mon, 3 Dec 2007 19:20:10 +0000 Ralf Baechle <ralf@linux-mips.org> wrote: > On Mon, Dec 03, 2007 at 09:56:11AM -0800, Andrew Sharp wrote: > > > arch/mips/mm/c-sb1.c | 70 > > ++++++++++++++++++++++++++++++++++ > > c-sb1.c does no longer exist. The functionality was folded into > c-r4k.c and at the same time alot of insanity aka pass 1 workarounds > dropped. Doh. I knew that, too. Mindlessly trying to clear my patch backlog... |
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