| To: | Andrew Sharp <andy.sharp@onstor.com> |
|---|---|
| Subject: | Re: [PATCH] Add code to determine the L2 cache size on Sibyte 1250/112x processors. |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Mon, 3 Dec 2007 19:20:10 +0000 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20071203175601.GA26533@onstor.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20071203175601.GA26533@onstor.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.17 (2007-11-01) |
On Mon, Dec 03, 2007 at 09:56:11AM -0800, Andrew Sharp wrote: > arch/mips/mm/c-sb1.c | 70 > ++++++++++++++++++++++++++++++++++ c-sb1.c does no longer exist. The functionality was folded into c-r4k.c and at the same time alot of insanity aka pass 1 workarounds dropped. Ralf |
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