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Re: WAIT vs. tickless kernel

To: ralf@linux-mips.org
Subject: Re: WAIT vs. tickless kernel
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Wed, 07 Nov 2007 23:23:43 +0900 (JST)
Cc: linux-mips@linux-mips.org
In-reply-to: <20071107.003925.74752709.anemo@mba.ocn.ne.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20071031163900.GB22871@linux-mips.org> <20071103.014649.122254137.anemo@mba.ocn.ne.jp> <20071107.003925.74752709.anemo@mba.ocn.ne.jp>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 07 Nov 2007 00:39:25 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> 
wrote:
> +     MFC0    k0, CP0_EPC
> +     ori     k0, 0x1f        /* 32 byte rollback region */
> +     xori    k0, 0x1f
> +     PTR_LA  k1, r4k_wait

Well, this part should be like this, for better pipelining.

        MFC0    k0, CP0_EPC
        PTR_LA  k1, r4k_wait
        ori     k0, 0x1f        /* 32 byte rollback region */
        xori    k0, 0x1f

> +     bne     k0, k1, 9f
> +     MTC0    k0, CP0_EPC
> +9:

And if we could assume branch-likely, this can be:

        .set    noreorder
        beql    k0, k1, 9f
         MTC0   k0, CP0_EPC
9:

But not sure if it really have points.

>       .align  5
> +BUILD_ROLLBACK_PROLOGUE handle_int
>  NESTED(handle_int, PT_SIZE, sp)

And one more question: should we put one more ".align 5" just befor
handle_int for CPUs do not need the rollback?

---
Atsushi Nemoto

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