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Re: WAIT vs. tickless kernel

To: ralf@linux-mips.org
Subject: Re: WAIT vs. tickless kernel
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 01 Nov 2007 01:31:24 +0900 (JST)
Cc: linux-mips@linux-mips.org
In-reply-to: <20071031161333.GA22871@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20071101.004906.106263529.anemo@mba.ocn.ne.jp> <20071031161333.GA22871@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 31 Oct 2007 16:13:33 +0000, Ralf Baechle <ralf@linux-mips.org> wrote:
> This one is definately playing with the fire.  Or alternatively requires
> detailed knowledge of the pipeline and pipelines tend to change.  MIPS
> Technologies does regular maintenance releases of its cores which also
> add features and may change the pipelines in subtle way that may break
> something like this.

Yes, I never think this is robust or guaranteed...

> The only safe but ugly workaround is to change the return from exception
> code to detect if the EPC is in the range startin from the condition
> check in the idle loop to including the WAIT instruction and if so to
> patch the EPC to resume execution at the condition check or the
> instruction following the WAIT.

I'm also thinking of this approach.  Still wondering if it is worth to
implement.

---
Atsushi Nemoto

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