| To: | "Maciej W. Rozycki" <macro@linux-mips.org> |
|---|---|
| Subject: | Re: [PATCH] c-r3k: Implement flush_cache_range() |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Mon, 29 Oct 2007 18:36:52 +0000 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <Pine.LNX.4.64N.0710171144410.28993@blysk.ds.pg.gda.pl> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <Pine.LNX.4.64N.0710171144410.28993@blysk.ds.pg.gda.pl> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.14 (2007-02-12) |
On Wed, Oct 17, 2007 at 11:51:39AM +0100, Maciej W. Rozycki wrote: > Contrary to the belief of some, the R3000 and related processors did have > caches, both a data and an instruction cache. Here is an implementation > of r3k_flush_cache_page(), which is the processor-specific back-end for > flush_cache_range(), done according to the spec in > Documentation/cachetlb.txt. > > While at it, remove an unused local function: get_phys_page(), do some > trivial formatting fixes and modernise debugging facilities. Applied. Ralf |
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