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Re: [PATCH] Use a sensible tlbex default for unknown CPUs

To: Thiemo Seufer <ths@networkno.de>
Subject: Re: [PATCH] Use a sensible tlbex default for unknown CPUs
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Fri, 26 Oct 2007 10:31:03 +0100 (BST)
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
In-reply-to: <20071025205654.GF3994@networkno.de>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20071025155912.GD3994@networkno.de> <Pine.LNX.4.64N.0710251707170.24086@blysk.ds.pg.gda.pl> <20071025205654.GF3994@networkno.de>
Sender: linux-mips-bounce@linux-mips.org
On Thu, 25 Oct 2007, Thiemo Seufer wrote:

> This is circular, as isa_level won't be initialized for a unknown CPU.
> The *_r2 check suggested by Ralf has the same problem AFAICS, so it
> looks like we have to stick with the original solution.

 Hmm, it looks like we have a misfeature in the probing code.  I think it 
would be reasonable to perform full discovery of features for all MIPS 
Architecture processors, even if the Company or Processor ID as reported 
by the PRId register is not a recognised one.  This is because for these 
processors we have all the necessary information about the privileged 
resource architecture implemented reported through the cp0 Config 
registers, including the type of the TLB and the topology of caches.  
With the revision 2 of the architecture, we also have the "ehb" and 
"jr.hb" instructions available to take care of cp0 hazards in a generic 
way.  So in a sense, we should be able to handle these processors 
correctly without the knowledge of what has been printed on their cases.

 Ralf's proposal is essentially the same code, except expressed a little 
bit differently, so no surprise it suffers from the same problem.

  Maciej

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