On Wed, Oct 17, 2007 at 08:34:52PM +0400, Sergei Shtylyov wrote:
> >>$ git-grep mips_timer_ack arch/mips
> >>arch/mips/dec/time.c: mips_timer_ack = dec_timer_ack;
> >>arch/mips/jmr3927/rbhma3100/setup.c: mips_timer_ack =
> >>jmr3927_timer_ack;
>
> TX3927 has three channel timer of which only channel 0 is used to
> implement a clocksource -- however, clocksource code whould also need to be
> changed since it's now jiffy-based and HRT doesn't tolerate this -- of
> course, if anybody still cared about this boards
>
> >>arch/mips/philips/pnx8550/common/time.c: mips_timer_ack =
> >>timer_ack;
>
> Here we have a case of a vendor abusing the count/compare register and
> also adding 3 more of them. One pair can be used for clockevents, the other
> for clocksource (its compare reg. being programmed to all ones).
Well, the TX3900 series is a bit of a frankenprocessor series. Like take
32-bits from here, a limb from the R3000 and TLB from that other processor
and at the end shock it all well - at TTL levels that is ;-) So it's not
quite obvious what to expect from that beast.
My question was mostly about the jmr3927 build failing with an undefined
reference to MIPS_CPU_IRQ_BASE. For most other systems failing with the
same issue it made sense to glue that by converting the platform to
irq_cpu. But if no device including the cp0 compare interrupt is directly
wired to the cp0 interrupt controller then enabling that doesn't make too
much sense. So I guess jmr3927 and a hand full of other systems want a
different fix.
Ralf
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