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Re: [MIPS] Probe for usability of cp0 compare interrupt.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [MIPS] Probe for usability of cp0 compare interrupt.
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 17 Oct 2007 18:03:35 +0100 (BST)
Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp>, linux-mips@linux-mips.org
In-reply-to: <20071017164636.GC5491@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <S20022491AbXJQLKE/20071017111004Z+82239@ftp.linux-mips.org> <20071018.011033.115643462.anemo@mba.ocn.ne.jp> <20071017164636.GC5491@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 17 Oct 2007, Ralf Baechle wrote:

> The two things are a know lose end.  There is a bug in some old MIPS
> processors where reading one of the compare or count registers in exactly
> the moment when both have identical values in the interrupt getting lost.
> 
> Will have to dig up the details on that one again before I can implement
> a proper workaround ...

 This is the erratum #53 of the R4000PC/SC processor and it triggers if 
the Count register is read.  Conveniently, in the errata sheet as 
distributed, the text is covered by a figure (Figure 1a on page 13), so 
you can only reach the page with some PostScript magic.  I did it a while 
ago and now have a separate document available which provides the text of 
page 13 with the figure removed.  I can provide it if there is interest.

  Maciej

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