Re: [MIPS] Probe for usability of cp0 compare interrupt.

[Atsushi Nemoto <anemo@mba.ocn.ne.jp>]

On Wed, 17 Oct 2007 12:09:59 +0100, linux-mips@linux-mips.org wrote:
> Author: Ralf Baechle <ralf@linux-mips.org> Tue Oct 16 23:20:48 2007 +0100
> Commit: b2c9797919e6997e284e30a1e6e443543eb7a1e1
> Gitweb: http://www.linux-mips.org/g/linux/b2c97979
> Branch: master
> 
> Some processors offer the option of using the interrupt on which
> normally the count / compare interrupt would be signaled as a normal
> interupt pin.  Previously this required some ugly hackery for each
> system which is much easier done by a quick and simple probe.

It seems write_c0_compare(0) will not work as expected if c0_count was
near 0xffffffff.  How about write_c0_compare(read_c0_compare()) (or
c0_timer_ack()) ?

Also something calculated from mips_hpt_frequency would be better than
the magic number 0x300000.

---
Atsushi Nemoto