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Re: [MIPS] Probe for usability of cp0 compare interrupt.

To: linux-mips@linux-mips.org
Subject: Re: [MIPS] Probe for usability of cp0 compare interrupt.
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 18 Oct 2007 01:10:33 +0900 (JST)
Cc: ralf@linux-mips.org
In-reply-to: <S20022491AbXJQLKE/20071017111004Z+82239@ftp.linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <S20022491AbXJQLKE/20071017111004Z+82239@ftp.linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 17 Oct 2007 12:09:59 +0100, linux-mips@linux-mips.org wrote:
> Author: Ralf Baechle <ralf@linux-mips.org> Tue Oct 16 23:20:48 2007 +0100
> Commit: b2c9797919e6997e284e30a1e6e443543eb7a1e1
> Gitweb: http://www.linux-mips.org/g/linux/b2c97979
> Branch: master
> 
> Some processors offer the option of using the interrupt on which
> normally the count / compare interrupt would be signaled as a normal
> interupt pin.  Previously this required some ugly hackery for each
> system which is much easier done by a quick and simple probe.

It seems write_c0_compare(0) will not work as expected if c0_count was
near 0xffffffff.  How about write_c0_compare(read_c0_compare()) (or
c0_timer_ack()) ?

Also something calculated from mips_hpt_frequency would be better than
the magic number 0x300000.

---
Atsushi Nemoto

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