linux-mips
[Top] [All Lists]

Re: [PATCH] enable PCI bridges in MIPS ip32

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] enable PCI bridges in MIPS ip32
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Fri, 5 Oct 2007 13:10:33 +0100 (BST)
Cc: Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>, linux-mips@linux-mips.org
In-reply-to: <20071004165546.GA23610@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <E1IdO0a-0000n7-Cg@eppesuigoccas.homedns.org> <Pine.LNX.4.64N.0710041316000.10573@blysk.ds.pg.gda.pl> <20071004130318.GC28928@linux-mips.org> <Pine.LNX.4.64N.0710041459270.10573@blysk.ds.pg.gda.pl> <20071004165546.GA23610@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Thu, 4 Oct 2007, Ralf Baechle wrote:

> It's documented somewhere in their specs.  Whatever, it ends crashing
> the system so device 31 is hands off.

 OK, found it -- it is the GT-64120A erratum FEr#19 leading to a hang of 
the device; perhaps we should mention it briefly in the source code.

 While the PCI spec says reads from the device #31, function #7 for host 
bridges implementing the recommended special cycle generation mechanism 
have undefined results, this behaviour is certainly "undefined" in a very 
silly way and then, according to the spec, it must not happen for the 
function #0, which is the only one probed by Linux by default for 
single-function devices.

  Maciej

<Prev in Thread] Current Thread [Next in Thread>