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Re: [PATCH] enable PCI bridges in MIPS ip32

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH] enable PCI bridges in MIPS ip32
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 4 Oct 2007 17:55:46 +0100
Cc: Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.64N.0710041459270.10573@blysk.ds.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <E1IdO0a-0000n7-Cg@eppesuigoccas.homedns.org> <Pine.LNX.4.64N.0710041316000.10573@blysk.ds.pg.gda.pl> <20071004130318.GC28928@linux-mips.org> <Pine.LNX.4.64N.0710041459270.10573@blysk.ds.pg.gda.pl>
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User-agent: Mutt/1.5.14 (2007-02-12)
On Thu, Oct 04, 2007 at 03:13:01PM +0100, Maciej W. Rozycki wrote:

> > I think historically we had something like chkslot() first in the code
> > for the Galileo/Marvell bridges where it's needed due the brainddead
> > abuse of device 31 - any access to that will crash the system.  From that
> > point on chkslot checking spread across the PCI code like the measles in
> > a kindergarden.
> 
>  Does the Galileo/Marvell do anything else with the device #31 than what 
> is recommended by the PCI spec as a way to issue special cycles?  We need 
> to be careful about the device #31 in general; it is seldom used anyway as 
> there are only 20 IDSEL lines defined by the standard and they are usually 
> mapped starting from the device #0.

It's documented somewhere in their specs.  Whatever, it ends crashing
the system so device 31 is hands off.

  Ralf

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