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Re: [Qemu-devel] QEMU/MIPS & dyntick kernel

To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Tue, 02 Oct 2007 22:57:24 +0200
Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org
In-reply-to: <20071002214826.7ee2fae8@the-village.bc.nu>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20071002200644.GA19140@hall.aurel32.net> <4702A99B.7020008@qumranet.com> <4702AC0F.1000906@aurel32.net> <20071002214826.7ee2fae8@the-village.bc.nu>
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Alan Cox a écrit :
>> Well on real hardware, the instruction rate and the timer are linked:
>> the timer run at half the speed of the CPU. As the corresponding
>> assembly code is very small, only uses registers and is run in kernel
>> mode, you know for sure that 48 cycles is more than enough.
> 
> What happens on NMI or if you take an ECC exception and scrubbing stall
> off the memory controller while loading part of that cache line of code
> into memory ?
> 

The code returns -ETIME, and the function is run again with the minimum
delay.

So as long as you don't have an exception every time, the code works.

-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

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