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Re: [Qemu-devel] QEMU/MIPS & dyntick kernel

To: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
Date: Tue, 2 Oct 2007 21:48:26 +0100
Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org
In-reply-to: <4702AC0F.1000906@aurel32.net>
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Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20071002200644.GA19140@hall.aurel32.net> <4702A99B.7020008@qumranet.com> <4702AC0F.1000906@aurel32.net>
Sender: linux-mips-bounce@linux-mips.org
> Well on real hardware, the instruction rate and the timer are linked:
> the timer run at half the speed of the CPU. As the corresponding
> assembly code is very small, only uses registers and is run in kernel
> mode, you know for sure that 48 cycles is more than enough.

What happens on NMI or if you take an ECC exception and scrubbing stall
off the memory controller while loading part of that cache line of code
into memory ?

Alan

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