| To: | David Daney <ddaney@avtrex.com> |
|---|---|
| Subject: | Re: MIPS atomic memory operations (A.K.A PR 33479). |
| From: | Daniel Jacobowitz <dan@debian.org> |
| Date: | Tue, 18 Sep 2007 22:32:35 -0400 |
| Cc: | Richard Sandiford <rsandifo@nildram.co.uk>, GCC Mailing List <gcc@gcc.gnu.org>, linux-mips@linux-mips.org |
| In-reply-to: | <46F06980.4080500@avtrex.com> |
| Mail-followup-to: | David Daney <ddaney@avtrex.com>, Richard Sandiford <rsandifo@nildram.co.uk>, GCC Mailing List <gcc@gcc.gnu.org>, linux-mips@linux-mips.org |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <46F06980.4080500@avtrex.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.15 (2007-04-09) |
On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote: > I guess my basic question is: Should MIPS_COMPARE_AND_SWAP have a 'sync' > after > the 'sc'? I would have thought that 'sc' made the write visible to all CPUs, > but on the SB1 it appears not to be the case. Yes, a barrier of some sort is definitely necessary. I believe the SB1 is weakly ordered, and the architecture spec permits both strong and weak ordering; but it's been a while since I tried this. -- Daniel Jacobowitz CodeSourcery |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | MIPS atomic memory operations (A.K.A PR 33479)., David Daney |
|---|---|
| Next by Date: | Re: MIPS atomic memory operations (A.K.A PR 33479)., Thiemo Seufer |
| Previous by Thread: | MIPS atomic memory operations (A.K.A PR 33479)., David Daney |
| Next by Thread: | Re: MIPS atomic memory operations (A.K.A PR 33479)., Thiemo Seufer |
| Indexes: | [Date] [Thread] [Top] [All Lists] |