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Re: MIPS atomic memory operations (A.K.A PR 33479).

To: David Daney <ddaney@avtrex.com>
Subject: Re: MIPS atomic memory operations (A.K.A PR 33479).
From: Daniel Jacobowitz <dan@debian.org>
Date: Tue, 18 Sep 2007 22:32:35 -0400
Cc: Richard Sandiford <rsandifo@nildram.co.uk>, GCC Mailing List <gcc@gcc.gnu.org>, linux-mips@linux-mips.org
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On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote:
> I guess my basic question is:  Should MIPS_COMPARE_AND_SWAP have a 'sync' 
> after 
> the 'sc'?  I would have thought that 'sc' made the write visible to all CPUs, 
> but on the SB1 it appears not to be the case.

Yes, a barrier of some sort is definitely necessary.  I believe the
SB1 is weakly ordered, and the architecture spec permits both strong
and weak ordering; but it's been a while since I tried this.

-- 
Daniel Jacobowitz
CodeSourcery

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