linux-mips
[Top] [All Lists]

O_DIRECT file access and cache aliasing...

To: linux-mips@linux-mips.org
Subject: O_DIRECT file access and cache aliasing...
From: David Daney <ddaney@avtrex.com>
Date: Tue, 28 Aug 2007 18:04:28 -0700
Cc: Johannes Schmidt <jschmidt@avtrex.com>, Steve Francis <sfrancis@avtrex.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Thunderbird 1.5.0.12 (X11/20070719)
We have a system based on a Sigam Designs SMP8634 processor (MIPS 4Kec). The caches are reported as:

Primary instruction cache 16kB, physically tagged, 2-way, linesize 16 bytes.
Primary data cache 16kB, 2-way, linesize 16 bytes.

Configured with CONFIG_DMA_NONCOHERENT.

When we write files that were opened with O_DIRECT set, we observe that there are many 16 byte chunks of data in the files that contain all zeros instead of the correct data.

My understanding is that the cache is virtually indexed. So I think what is happening is that when data is written to memory by a user application that does an O_DIRECT write, the IDE driver is given a list of pages to transfer to the disk. The driver then does a dma_cache_wback() on the KSEG0 address of the pages before initiating the DMA operation. Since the KSEG0 address and the USEG address of the physical memory are different, the data is never flushed to memory resulting in incorrect data being written to disk.

Two questions:

1) Does this analysis seem plausible?

2) How do I fix it given that I cannot change the hardware?

Several possibilities come to mind:

A) Don't use O_DIRECT mode.

B) Hack up sys_read and sys_write to flush the USEG addresses when CONFIG_DMA_NONCOHERENT *and* O_DIRECT are in effect.

Any helpful advice would be welcome,
David Daney


<Prev in Thread] Current Thread [Next in Thread>