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Re: Context switches & interrupts affecting cache?

To: Mohamed Bamakhrama <bamakhrama@gmail.com>
Subject: Re: Context switches & interrupts affecting cache?
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 3 Aug 2007 13:40:23 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <40378e40708030359h3729e4b1m5390c258b29d6ae0@mail.gmail.com>
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References: <40378e40708030359h3729e4b1m5390c258b29d6ae0@mail.gmail.com>
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On Fri, Aug 03, 2007 at 12:59:41PM +0200, Mohamed Bamakhrama wrote:

> Hi all,
> I have one question regarding context switches between user and kernel
> modes and interrupts. Do they invalidate the I-cache or D-cache?

Never on MIPS.

I call an architecture that would require a cacheflush for such a
context switch totally broken and yes, they exist - but nothing from
the MIPS family.

  Ralf

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