| To: | Mohamed Bamakhrama <bamakhrama@gmail.com> |
|---|---|
| Subject: | Re: Context switches & interrupts affecting cache? |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Fri, 3 Aug 2007 13:40:23 +0100 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <40378e40708030359h3729e4b1m5390c258b29d6ae0@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <40378e40708030359h3729e4b1m5390c258b29d6ae0@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.14 (2007-02-12) |
On Fri, Aug 03, 2007 at 12:59:41PM +0200, Mohamed Bamakhrama wrote: > Hi all, > I have one question regarding context switches between user and kernel > modes and interrupts. Do they invalidate the I-cache or D-cache? Never on MIPS. I call an architecture that would require a cacheflush for such a context switch totally broken and yes, they exist - but nothing from the MIPS family. Ralf |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: Kernel space access to 2GB of physical memory, Ralf Baechle |
|---|---|
| Next by Date: | Re: Context switches & interrupts affecting cache?, Mohamed Bamakhrama |
| Previous by Thread: | Context switches & interrupts affecting cache?, Mohamed Bamakhrama |
| Next by Thread: | Re: Context switches & interrupts affecting cache?, Mohamed Bamakhrama |
| Indexes: | [Date] [Thread] [Top] [All Lists] |