On Thu, 2 Aug 2007, Sergei Shtylyov wrote:
> Yeah, that the format of type 1 cycles.
Well, that is how it is presented to software on many systems. The type
1 cycle format actually differs a little bit, as the two least significant
bits of the register number are passed to byte enables and when presented
to the bus they are replaced with a fixed code that denotes the cycle
type.
> Unfortunately, Alchemy designers were too lazy to implement a simple
> translation scheme for type 0 cycles. They probably though that with 36-bit
> bus the may not limit themselves... :-)
Yes, some people seem to think the abundance of resources exempts them
from properly architecting their designs, sigh...
On the other hand, the decision to identity-map the PCI config space in
the physical address space of the processor rather than only making it
accessible through a pair of an address and a data register was good IMO.
Maciej
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