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Re: Modpost warning on Alchemy

To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Subject: Re: Modpost warning on Alchemy
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 1 Aug 2007 17:54:37 +0100 (BST)
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <46B0B6B4.5090103@ru.mvista.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20070801115231.GA20323@linux-mips.org> <46B07B36.1000501@ru.mvista.com> <Pine.LNX.4.64N.0708011337390.20314@blysk.ds.pg.gda.pl> <46B086EB.2030101@ru.mvista.com> <46B0880B.2000009@ru.mvista.com> <Pine.LNX.4.64N.0708011629010.20314@blysk.ds.pg.gda.pl> <46B0AA74.7040100@ru.mvista.com> <Pine.LNX.4.64N.0708011708250.20314@blysk.ds.pg.gda.pl> <46B0B6B4.5090103@ru.mvista.com>
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On Wed, 1 Aug 2007, Sergei Shtylyov wrote:

> > And regarding what you have written above and the size issue you mentioned
> > in another e-mail (do you map the whole PCI config space linearly in the
> > physical address space of the CPU or suchlike?) -- PCI 
> 
>    No, I don't.  But that was why the original code preferred the wired entry
> approach over ioremap() -- not to map a whole range...

 So what is the issue with the size then?  How big is the area?

> > config space accesses are rare (by design rather than chance), so 
> 
>    That depends on the drivers used (some IDE drivers access it really often).

 It is their problem I would say -- there is a design problem either in 
these drivers or the hardware handled.  The PCI spec is very explicit that 
the config space is meant to be seldom accessed only.  Device 
initialization/shutdown and bus error recovery are the normal places.

> > performance is a non-issue and it should be absolutely fine for you to call
> > ioremap() and iounmap() in code specific for your PCI host bridge for the
> > required fragment upon every access.  There is no need for a permanent 
> 
>    That's an idea -- however, as the currecnt code uses a cached mapping, this
> part would certainly need to be saved in the new implementaion -- if someone
> will go and fix it eventually. :-)

 Well, cached mapping does not seem particularly wise with PCI 
configuration registers, but you have got the ioremap_cachable() call if 
you insist. ;-)

> > Well, more about Linux perhaps than MIPS in general. :-)
> 
>    Let's say that was about Linux/MIPS.  But the key word was "wasting". ;-)

 I reckon the key is how you look at it. ;-)

  Maciej

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