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Re: Modpost warning on Alchemy

To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: Modpost warning on Alchemy
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 1 Aug 2007 16:49:14 +0100 (BST)
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>, Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <20070801163926.038c48db@the-village.bc.nu>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20070801115231.GA20323@linux-mips.org> <46B07B36.1000501@ru.mvista.com> <Pine.LNX.4.64N.0708011337390.20314@blysk.ds.pg.gda.pl> <46B086EB.2030101@ru.mvista.com> <20070801163926.038c48db@the-village.bc.nu>
Sender: linux-mips-bounce@linux-mips.org
On Wed, 1 Aug 2007, Alan Cox wrote:

> > >  Of course it will.  It shall work with whatever physical address space 
> > > is 
> > > supported by your MMU.  As long as the MMU is handled correctly that is, 
> > > but I guess I may have omitted this clarification as obvious.
> > 
> >     Even on a CPU with 36-bit physical address? ;-)
> 
> Nope. This is one problem for example with ioremap on a Pentium Pro.

 Well, but we only consider MIPS processors here which do not have such 
odd restrictions resulting from bad design decisions in the past. ;-)  
The 32-bit TLB entry format allows for up to 36 bits of the physical 
address space (34 bits if support for the page size of 1kB has been 
enabled).  For anything beyond that you need a 64-bit MIPS processor using 
the 64-bit TLB entry format.

  Maciej

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