| To: | ths@networkno.de |
|---|---|
| Subject: | Re: [PATCH] tx49xx: add some mach specific headers |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Wed, 25 Jul 2007 12:32:36 +0900 (JST) |
| Cc: | sshtylyov@ru.mvista.com, linux-mips@linux-mips.org, ralf@linux-mips.org |
| In-reply-to: | <20070724212034.GA26960@networkno.de> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20070725.015008.78730579.anemo@mba.ocn.ne.jp> <46A6302A.5010105@ru.mvista.com> <20070724212034.GA26960@networkno.de> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Tue, 24 Jul 2007 22:20:34 +0100, Thiemo Seufer <ths@networkno.de> wrote: > >> +#define cpu_has_mips32r1 0 > >> +#define cpu_has_mips32r2 0 > >> +#define cpu_has_mips64r1 0 > >> +#define cpu_has_mips64r2 0 > > > > Hm, really? > > IIRC it is MIPS IV. (tx99 is MIPS64R1). It is MIPS III. --- Atsushi Nemoto |
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