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Re: O2 RM7000 Issues

To: Sergey Rogozhkin <rogozhkin@niisi.msk.ru>
Subject: Re: O2 RM7000 Issues
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 17 Jul 2007 13:27:11 +0100
Cc: Linux MIPS List <linux-mips@linux-mips.org>, "Gleb O. Raiko" <raiko@niisi.msk.ru>, Kumba <kumba@gentoo.org>
In-reply-to: <469C8600.7090208@niisi.msk.ru>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4687DCE2.8070302@gentoo.org> <468825BE.6090001@gmx.net> <50451.70.107.91.207.1183381723.squirrel@webmail.wesleyan.edu> <20070704152729.GA2925@linux-mips.org> <20070704192208.GA7873@linux-mips.org> <469C8600.7090208@niisi.msk.ru>
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User-agent: Mutt/1.5.14 (2007-02-12)
On Tue, Jul 17, 2007 at 01:04:00PM +0400, Sergey Rogozhkin wrote:

> >for E9000 platforms.
> 
> Are you really sure RM7000 has this bug? Workaround mentioned above 
> breaks gcc signal frame unwinding mechanism: it search for sigcontext 
> struct at fixed offset from signal trampoline.
> 
> And one another known RM7000 bug, maybe not taken into account by linux: 
> errata 38. r4k_wait is not suitable for RM7000 on some systems. I don't 
> know if "O2" is affected.

The fingerprint of this bug would be write data getting corrupted to
contain its physical address instead.  I haven't seen such bug reports
ever but a hand full cycles of latency to the idle loop sounds like the
safe thing.  Untested fix below.

What's really astonishing about this is that affects basically the entire
QED family of processors - R4600, R4700, R4640, R5000, RM52xx and RM7000.

Which also is yet again empirical proof for the WAIT instruction being
hard to get right ...

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f599e79..7ee0cb0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -75,6 +75,26 @@ static void r4k_wait_irqoff(void)
        local_irq_enable();
 }
 
+/*
+ * The RM7000 variant has to handle erratum 38.  The workaround is to not
+ * have any pending stores when the WAIT instruction is executed.
+ */
+static void rm7k_wait_irqoff(void)
+{
+       local_irq_disable();
+       if (!need_resched())
+               __asm__(
+               "       .set    push            \n"
+               "       .set    mips3           \n"
+               "       .set    noat            \n"
+               "       mfc0    $1, $12         \n"
+               "       sync                    \n"
+               "       mtc0    $1, $12         \n"
+               "       wait                    \n"
+               "       .set    pop             \n");
+       local_irq_enable();
+}
+
 /* The Au1xxx wait is available only if using 32khz counter or
  * external timer source, but specifically not CP0 Counter. */
 int allow_au1k_wait;
@@ -132,7 +152,6 @@ static inline void check_wait(void)
        case CPU_R4700:
        case CPU_R5000:
        case CPU_NEVADA:
-       case CPU_RM7000:
        case CPU_4KC:
        case CPU_4KEC:
        case CPU_4KSC:
@@ -142,6 +161,10 @@ static inline void check_wait(void)
                cpu_wait = r4k_wait;
                break;
 
+       case CPU_RM7000:
+               cpu_wait = rm7k_wait_irqoff;
+               break;
+
        case CPU_24K:
        case CPU_34K:
                cpu_wait = r4k_wait;

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