On Wed, 11 Jul 2007, Maciej W. Rozycki wrote:
> > > You can still dispatch interrupts manually by examining the IRR register,
> > > but having a way to ask the 8259A's prioritiser would be nice. Although
> > > given such a lethal erratum you report I would not count on the
> > > prioritiser
> > > to provide any useful flexibility...
> > >
> > yeah, that's a straight thought, tried but failed:(, patch followed.
> You may have to modify other functions from arch/mips/kernel/i8259.c;
> yes, this makes the whole experience not as pretty as one would hope...
BTW, have you considered skipping the whole 8259A legacy burden and using
the interrupt mapper directly? From a brief look at the datasheet I
conclude you should be able to OR all the interrupt lines to a single
8259A input (say IRQ0 for the sake of this consideration -- it does not
matter), set it to the level triggered mode, mask all the 8259A inputs but
this one and ignore the device from then on.
It would work as a "virtual wire", using the Intel's terminology, with
its INT output simply following its IR0 input. You can type:
$ grep '8259A Virtual Wire' arch/i386/kernel/io_apic.c
for a reference; ;-) you can skip the AEOI setup as in a system based on a
MIPS processor an INTA cycle will be unlikely to reach the 8259A by
accident (which may happen in the wild world of broken PCs) -- which you
have learnt the hard way by now already.
You can then dispatch interrupts based on the interrupt mapper registers
which has this nice side effect of much of the sharing having been
removed. It will not work with edge-triggered interrupts, but you do not
need that 8254 timer, do you?