On Wed, Jul 04, 2007 at 04:27:29PM +0100, Ralf Baechle wrote:
> R5000, RM5200 and RM7000 are all MIPS IV processors so have the same
> instruction set. That leaves the usual suspects - pipeline hazards,
> cache problems and CPU bugs to research.
Big loud bell began ringing. The RM7000 fetches and decodes multiple
instructions in one go. And just like the E9000 cores it does
throw an exception if it doesn't like one of the opcodes even if that
doesn't actually get executed. The kernel has a workaround for this
PMC-Sierra peculiarity (I call it a bug) but it's only being activated
for E9000 platforms.