Maciej W. Rozycki wrote:
I don't see how you can have hrtimer support if you choose a periodic
Well, periodic timers do seem to work somehow for everybody else with no
Except the purely periodic timers can't serve as HRT (unless one cheats
and also declares them as one-shot).
starting from the DEC code I referred to and including
other platforms, like the i386, which uses the 8254 for the timer
interrupt and as a HPT, by default, the very same counter or the TSC in
What do you mean by HPT -- clocksource?
the CPU if available or, I think, some chipset timer, because some
Weel there was ACPI timer (32-bit free running counter, IIRC) -- but
somehow I was unable to find the code for it in the current source. And there
is HPET which is indeed preferred over broken TSC.
brilliant soul decided to break the TSC at one point.
Note that the 8254 can be reprogrammed into a one-shot mode, but somehow
nobody does it. ;-)
Well, hrtimers can do it but the LAPIC timer is preferred over 8254.
Similarly for the local APIC timer that is used for
scheduling on i386 systems (if available).
LAPIC timer is also used for HRT, i.e. in one-shot mode (simply because
it's the best choice for such purpose -- HRTs are per-CPU).
mips_timer_state appropriately, i.e. to flip at the HZ rate (it may be
based on one of the south bridge choices mentioned above or some
free-running counter for example), but people seem to prefer to write
their own code for some reason. ;-)
Do you have any examples in mind which rewrite their own calibration
code ? I'm too lazy to search into all board code.
See arch/mips/mips-boards/generic/time.c for example. Or any platform
that uses the CP0 timer interrupt and has a configurable CPU frequency --
you can find them easily by looking for ones that calculate
mips_hpt_frequency rather than set it to a fixed value.
Alchemy for one.