| To: | ralf@linux-mips.org |
|---|---|
| Subject: | Re: Tickless/dyntick kernel, highres timer and general time crapectomy |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Fri, 08 Jun 2007 23:22:43 +0900 (JST) |
| Cc: | vagabon.xyz@gmail.com, sshtylyov@ru.mvista.com, linux-mips@linux-mips.org |
| In-reply-to: | <20070607154801.GG26047@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <46680B75.5040809@ru.mvista.com> <cda58cb80706070744v21e1bbf3sa28990b4477a8844@mail.gmail.com> <20070607154801.GG26047@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Thu, 7 Jun 2007 16:48:01 +0100, Ralf Baechle <ralf@linux-mips.org> wrote: > But even if so, the basic solution is the same - just ignore the interrupt > whenever it happens to be triggered. Or if it isn't shared with an > active performance counter interrupt, you could even disable_irq() it. Using disable_irq() on the counter/compare interrupt might make the WAIT instruction really not wait on some chips. It is implementation dependent wheather an assertion of masked interrupt break the WAIT instruction or not. Busy looping in cpu_idle() would not preferred, but I'm not sure this is really a problem yet. Maybe I should have closer look at dyntick. --- Atsushi Nemoto |
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