On Mon, 9 Apr 2007, Thomas Bogendoerfer wrote:
> > To me, it doesn't make much sense with or without reading the code.
> > And note that no other boards claim ports 0x0000 thru 0x0fff to PCI.
> no other board MIPS board has EISA behind PCI afaik. So this is a new
To everybody involved: quite a few Alpha boxes use the PCEB bridge, which
may or may not be the same as in here, so they may be used as a reference
of how things may be set up. Though, being quite an old port, this code
may not necessarily represent the best approach possible.
Personally I think ISA and EISA resources that are behind a PCI bus (or
any other, for that matter) should be registered as descendants to that
bus. It's only the PC architecture that makes (E)ISA resources special --
almost any other platform will relocate them arbitrarily (they will not
start from zero in the host address space, which may even have no notion
of the I/O address space at all) and may have multiple copies if multiple
PCI buses are used in a non-tree configuration. It may be useful to
register PCI I/O windows in the MMIO space as appropriate too.
Also mapping PCI I/O addresses from 0 does make sense in some actual
hardware configurations which do not have any legacy bridges involved, so
making sure code is prepared to do this is not an unreasonable thing to
do. There is currently (or used to be, not so long ago) a problem with
some code somewhere as I tried such a setup with a SWARM board and I
recall getting a failure somewhere, which I mean to get back to at one