|To:||Marco Braga <firstname.lastname@example.org>|
|Subject:||Re: Au1500 and TI PCI1510 cardbus|
|From:||Sergei Shtylyov <email@example.com>|
|Date:||Mon, 19 Mar 2007 15:36:06 +0300|
|Cc:||Michael Stickel <firstname.lastname@example.org>, email@example.com|
|Organization:||MontaVista Software Inc.|
|References:||<firstname.lastname@example.org> <45FBB9C7.email@example.com> <firstname.lastname@example.org> <45FBF0F1.email@example.com> <firstname.lastname@example.org>|
|User-agent:||Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803|
Marco Braga wrote:
I am sory, I meant the datasheet of the Au1500. I do not find the paragraph anymore, but can tell you more on monday.
I think Michael actually mean the specification update, not datasheet. Indeed, errata 32
Thank you. I've checked the data book but I've not found anything so explicit. Paragraph 4.3.10 "Other notes" states:
"The Au1500 PCI contoller cannot be used with external PCI-to-PCI bridges that have PCI bus-mastering devices on the secondary bus which target the Au1500 memory."
But this is not exactly an explanation.. I've found nothing regarding race conditions or delayed transactions. I'll wait eagerly for monday when all the truths will be revealed. :)
Hrm, this seems enough of an explanation -- it basically says that you can't use any decent PCI device behind the bridge. The abovementioned errata tells that "any mastering device on the other side of a P2P bridge, where the target is the Au1500 processor, will eventually lead to a lock-up condition of the PCI bus or even the entire system".
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