All MIPS Release 2 implementations contain the EBase register.
/gmu
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Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc. Email: uhler AT mips.com
1225 Charleston Road Voice: (650)567-5025
Mountain View, CA 94043
> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Marc St-Jean
> Sent: Wednesday, February 28, 2007 1:36 PM
> To: Ralf Baechle
> Cc: Thiemo Seufer; Andrew Sharp; linux-mips@linux-mips.org
> Subject: Re: [PATCH 2/5] mips: PMC MSP71xx mips common
>
>
>
> Ralf Baechle wrote:
> > On Tue, Feb 27, 2007 at 05:38:41PM +0000, Thiemo Seufer wrote:
> >
> > > Something like
> > >
> > > #if LOADADDR == 0xffffffff80000000
> > > .fill 0x400
> > > #endif
> > >
> > > but by defining an appropriate name in
> arch/mips/Makefile instead
> > of > externalizing the load-y/LOADADDR there.
> >
> > Basically a good idea but it will fail for 64-bit kernels
> so the test
> > would need to be extended to cover XKPHYS as well. Also R2
> processors
> > which have the c0_ebase registers do no need to reserve space for
> > exception handlers as they can easily move them elsewhere.
> >
> > Ralf
>
> Hi Ralf,
>
> From your description it sounds like not all R2 CPUs have
> c0_ebase registers?
>
> I don't know how to check for c0_ebase from the
> pre-processor, the test below assumes they all do.
>
> How about something like:
>
> #if (defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) && \
> VMLINUX_LOAD_ADDRESS == CKSEG0) || \
> ((defined(CONFIG_SYS_HAS_CPU_MIPS64_R1) ||
> defined(CONFIG_SYS_HAS_CPU_MIPS64_R2)) && \
> VMLINUX_LOAD_ADDRESS == XKPHYS)
> .fill 0x400
> #endif
>
> Marc
>
>
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