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RE: Uncached mmap

To: <linux-mips@linux-mips.org>
Subject: RE: Uncached mmap
From: "Mile Davidovic" <Mile.Davidovic@micronasnit.com>
Date: Mon, 13 Nov 2006 16:30:26 +0100
Cc: "'Ralf Baechle'" <ralf@linux-mips.org>
In-reply-to: <20061113123233.GA20337@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Thread-index: AccHH9YOr1x418tdT9Clo10n00/ztgAA+0+Q
Hello again,
first I want to thank You for Your fast answer. I work on MIPS 4Kec with linux
kernel in version 2.6.15 from linux-mips (gcc 4.0.3 and gcc 3.4.3).

>> There is no byte access to uncached mmaped memory. Is this correct statement?
>Definately wrong.  For example alot of mmapped I/O devices use uncached
>byte accesses.

Ok, in that case I have problem with byte access on mmaped uncached memory. 
Reason for previous post is next:
If I write bytes to mmaped uncached memory like:
...
ptr = (unsigned char*)mmap(0,lineSize,PROT_READ|PROT_WRITE,MAP_SHARED,fd0,0);
...
for (i = 0; i < 12; i++) 
   *ptr++ = 0xaa;

this loop will not write all bytes correctly (every 4 bytes will have 0xaa as
value), here is dump from Lauterbach debugger:
___address__|_0________4________8________C________0123456789ABCDEF
  D:83660000|>FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
  D:83660010| 000000AA 000000AA 000000AA 0000AA02 ................

and if I use bigger loop
for (i = 0; i < 20; i++) 
   *ptr++ = 0xaa;
My linux will be crashed on 13 write. So, this is reason why I thought that
byte access is not allowed on mmaped uncached memory. 

Is it possible that problem with byte access is related with device mmap
function?

>This stament if of course limited to the CPU's part of the system.  Devices
>may have their specific restrictions on access size and its not uncommon to
>have such restrictions though that would seem unlikely for framebuffer
>memory.

Ok, I understood this.

>If your particular CPU support it you may want to use cache mode "uncached
>accellerated" for a framebuffer.  It should deliver significtn performance
>gains yet avoid the need for cache flushes.



Thanks in advance
Mile


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