| To: | macro@linux-mips.org |
|---|---|
| Subject: | Re: [PATCH] fast path for rdhwr emulation for TLS |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Mon, 11 Sep 2006 23:30:46 +0900 (JST) |
| Cc: | nigel@mips.com, ralf@linux-mips.org, dan@debian.org, linux-mips@linux-mips.org |
| In-reply-to: | <Pine.LNX.4.64N.0609111406400.29692@blysk.ds.pg.gda.pl> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> <Pine.LNX.4.64N.0609111406400.29692@blysk.ds.pg.gda.pl> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Mon, 11 Sep 2006 14:09:20 +0100 (BST), "Maciej W. Rozycki" <macro@linux-mips.org> wrote: > > But I'm still looking for better solution (silver bullet?) for > > cpu_has_vtag_icache case. > > What's wrong with just letting a TLB fault happen? It might add a little overhead to usual TLB refill handling. The overhead might be neglectable, but I'm not sure. --- Atsushi Nemoto |
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