| To: | ralf@linux-mips.org |
|---|---|
| Subject: | Re: cpu_idle and cpu_wait |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Sun, 10 Sep 2006 21:52:52 +0900 (JST) |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20060910001803.GA826@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20051118.122242.07017522.nemoto@toshiba-tops.co.jp> <20060608.010901.108121387.anemo@mba.ocn.ne.jp> <20060910001803.GA826@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Sun, 10 Sep 2006 02:18:03 +0200, Ralf Baechle <ralf@linux-mips.org> wrote: > Applied but based on feedback from the 4K and 5K CPU designers I modified > your patch to continue using the old code. Thanks! IIRC MIPS4K? and MIPS5Kc datasheets state that any masked interrupts can break WAIT instruction, but I could not test by myself since I do not have any of them. I believe feedback from CPU designers of course :-) --- Atsushi Nemoto |
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