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Re: [PATCH] au1x00 serial real interrupt

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] au1x00 serial real interrupt
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Date: Tue, 05 Sep 2006 19:19:35 +0400
Cc: Rodolfo Giometti <giometti@linux.it>, linux-mips@linux-mips.org, rmk+serial@arm.linux.org.uk
In-reply-to: <20060522165244.GA16223@enneenne.com>
Organization: MontaVista Software Inc.
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060522165244.GA16223@enneenne.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803
Hello.

Rodolfo Giometti wrote:

Here my patch to enable real interrupts management for the au1x00
CPUs.

------------------------------------------------------------------------

diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 7b23664..0197062 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -11,6 +11,14 @@
#include <linux/config.h> +#ifdef CONFIG_SOC_AU1X00
+/*
+ * We have to redefine "is_real_interrupt()" for Au1x00 CPUs...
+ */
+#undef is_real_interrupt
+#define is_real_interrupt(irq) ((irq) != ~0)
+#endif
+
 /*
  * This assumes you have a 1.8432 MHz clock for your UART.
  *

Ralf, how about this patch? Can it be applied, at least 3 months after posting? Alchemy UART0 uses IRQ0 and 0 is treated as "no IRQ" by drivers/serial/8250.c which says the macro should be redefined in <asm/serial.h> if needed.

WBR, Sergei

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