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Re: [PATCH] TX49 has write buffer

To: sshtylyov@ru.mvista.com
Subject: Re: [PATCH] TX49 has write buffer
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Sat, 19 Aug 2006 23:11:32 +0900 (JST)
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, mlachwani@mvista.com
In-reply-to: <44E64687.7000704@ru.mvista.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <44E64687.7000704@ru.mvista.com>
Sender: linux-mips-bounce@linux-mips.org
On Sat, 19 Aug 2006 03:00:23 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> 
wrote:
> TX49 CPUs have a write buffer, so we need to select CPU_HAS_WB -- otherwise 
> all Toshiba RBTX49xx kernels fail to build.

TX49 CPUs also have a SYNC instruction which flushes a write buffer.
I think it is enough and wbflush() have been abused in
arch/mips/tx4927/ and arch/mips/tx4938/ codes.

There is old thread about this issue:

http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=Pine.GSO.3.96.1030415161611.13254H-100000%40delta.ds2.pg.gda.pl

---
Atsushi Nemoto

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