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Re: pseudo 32 bit physical addresses and the real 36 bit world

To: Freddy Spierenburg <freddy@dusktilldawn.nl>
Subject: Re: pseudo 32 bit physical addresses and the real 36 bit world
From: Dan Malek <dan@embeddedalley.com>
Date: Wed, 19 Jul 2006 12:22:10 -0400
Cc: linux-mips@linux-mips.org
In-reply-to: <20060719155804.GB5162@dusktilldawn.nl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20060719155804.GB5162@dusktilldawn.nl>
Sender: linux-mips-bounce@linux-mips.org

On Jul 19, 2006, at 11:58 AM, Freddy Spierenburg wrote:

The AU1100 processor uses internally a 36-bit address bus. The
kernel (32 bits) is only able to work with 32-bit addresses.
Well, there must exist some sort of scheme for the kernel to work
with these 36-bit addresses, but I don't quiet get it yet. Is
anybody willing to give me some insight?

On the Alchemy processors, only some peripherals exist
above the 32-bit boundary.  We use a 64-bit version of
ioremap() to access this space.

Of course the compiler warns us during compilation of
drivers/pcmcia/au1000_generic.c:

drivers/pcmcia/au1000_generic.c:403: warning: integer constant is too large for "long" type

It looks like your configuration file is not enabling the
64-bit IO option.

....  I expect
from reading the au1100 databook and 'See MIPS Run (chapter 6)
that the TLB is involved, but I'm not yet able to link it
altogether.

This has already been done for you :-)  There is nothing
for you to invent.  You didn't mention which version of
the kernel you are using, but the default configuration
files for boards with Alchemy processors should have
all of this properly configured.

Thanks.

        -- Dan


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